 Complian with Universal Serial Bus specification Revision 2.0 (Data Rate 1.5/12/480Mbps) |
|
Compliant with Open Host Controller Interface specification for USB Rev 1.0a |
|
Compliant with Enganced Host Controller Interface specification for USB Rev 0.95 |
PCI multi-function device consists of two OHCI Host Controller cores for full/low-speed signaling
 and one EHCI Host Controller cores for high-speed signaling |
Root Hub with 5 (max.) downstream facing ports which are shared by OHCI and EHCI Host
Controller core |
All downstream facing ports can handle high-speed (480Mbps), full-speed (12Mbps), and low-speed
(1.5Mbps) transaction |
|
Configurable number of downstream facing ports (2 to 5) |
|
32-bit 33MHz host interface compliant to PCI specification release 2.2 |
|
PCI Bus bus-master access |
|
System Clock is generated by 30MHz X'tal or 48MHz clock input |
|
Ooerational registers direct-mapped to PCI memory space |
Legacy support for all downstream facing ports. Legacy support features allow easy migration for
motherboard implementation |
|
3.3V power supply, PCI signal pins have 5V tolerant circuit |
